How to Build an Always-On Vision Device with RV1106

Sep 09, 2026

In unattended vision IoT applications powered by batteries or solar photovoltaic systems, it is difficult for devices to achieve both ultra-long standby time and real-time controllable connectivity. This is a key bottleneck limiting the large-scale deployment of outdoor environmental monitoring, general security, and unattended industrial inspection projects.

Deep-sleep solution: The device disconnects from the network and suspends services while asleep. Battery life is excellent, but the cloud cannot issue commands for remote inspection, image capture, or parameter configuration. Sudden events such as unauthorized entry, abrupt water-level changes, or equipment movement cannot be captured, creating monitoring blind spots and preventing the system from meeting operational reliability requirements.
Continuous full-load solution: The device remains connected and continuously captures high-definition video, supporting real-time cloud interaction and complete event recording. However, system power consumption is high, lithium-battery runtime is short, on-site charging and maintenance are frequent, and operating costs for outdoor deployment are high. This approach is unsuitable for long-term unattended operation.

To address these industry challenges, Rockchip introduced the RV1106 series of vision-processing SoCs for AIoT vision applications. The chips integrate a CPU, NPU, ISP, and video codec engine for low-power, cost-sensitive embedded vision AI devices. Applications include battery-powered security cameras, agricultural and forestry monitoring, water-conservancy station monitoring, and unattended industrial inspection.

RV1106 Series Specifications

Functional Module	Architecture Specifications and Performance	Engineering Value
CPU and MCU	Single-core 32-bit ARM Cortex-A7 processor with NEON and FPU. It has 32KB I-Cache, 32KB D-Cache, a unified 128KB L2 cache, and an independent MCU with 16KB cache. The official manual does not specify a clock frequency; a typical SDK configuration is 1.2 GHz. Heterogeneous scheduling assigns the main application to the A7 and low-power real-time interrupts to the MCU. During sleep, the A7 can be powered down while only the MCU remains active. Performance depends on the power-domain strategy.	Supports the AOV low-power sleep-and-wake mechanism, balancing system computing performance with battery life.
NPU	Hardware neural-network accelerator supporting mixed INT4, INT8, and INT16 quantization and model conversion from TensorFlow, PyTorch, Caffe, TFLite, and ONNX-NN. The theoretical peak performance is 1 TOPS. Practical performance is approximately 0.5 TOPS on RV1106G2, while RV1106G3 can deliver the full 1 TOPS. Inference performance is limited by memory capacity, bandwidth, and model size.	Runs local edge AI for human detection, object detection, and face recognition. Hardware acceleration reduces CPU load and removes the need for cloud computing.
ISP	Hardware ISP with two MIPI-CSI/LVDS inputs and one DVP input, supporting up to three cameras. Image-processing functions include HDR-MGE, 3DNR/2DNR, 3A, LSC, defogging, and distortion correction. RV1106G2 supports up to 5M@30FPS. RV1106G3 and RV1106 support up to 8M@15FPS. Frame rate is constrained by bandwidth, power consumption, and the encoding path.	Preprocesses images under complex lighting and outputs high-quality YUV streams for encoding and AI inference, reducing software image-processing load.
VENC Video Encoder	Hardware encoding engine supporting H.264 High Profile, H.265 Main Profile, and JPEG, with six rate-control modes and a maximum bit rate of 60 Mbps. RV1106G2 supports 5MP at 30 FPS; RV1106G3 and RV1106 support up to 8MP at 15 FPS. JPEG capture supports up to 4MP at 60 FPS, with multiple output streams.	Hardware compression frees CPU resources for security functions such as multi-stream preview, local recording, and event capture.
RKIVE Intelligent Video Engine	Dedicated hardware vision-processing unit with GMM, Canny, CCL, optical-flow, filtering, and morphology operators. Motion detection and foreground segmentation run in hardware with minimal CPU use. Processing frame rate follows the ISP output limit.	Implements scene-change detection and foreground extraction in hardware, reducing CPU overhead for image-change detection in low-power AOV operation.
Memory Subsystem	RV1106G2 integrates 1Gb (128MB) DDR3L in the SIP. RV1106G3 integrates 2Gb (256MB) DDR3L in the SIP. The BGA version of RV1106 supports external 16-bit DDR2, DDR3, DDR3L, or DDR4 up to 1024MB. G2 and G3 memory is fixed and cannot be expanded. High resolution, multiple cameras, and large models are limited by memory capacity and bandwidth, while the BGA version allows flexible memory selection.	The SIP solution eliminates external DDR devices and PCB routing, reducing BOM cost. The BGA version supports multi-camera systems and advanced vision equipment running complex algorithms.
Power Management	Multiple isolated power domains support independent power-domain switching and multiple sleep and wake-up sources. The datasheet provides no official power figures. Engineering measurements show approximately 500 mW during full-function operation and approximately 40 mW in AOV standby. Earlier estimates of 0.8 W and 0.1 W must be replaced with measurements from the production prototype.	Supports runtime evaluation for lithium-battery and solar-powered products and helps define power-domain switching strategies for low-power AOV operation.
Package	RV1106G2/G3 use a 12.3 x 12.3 mm QFN128 package with 0.35 mm pin spacing and an MSL3 rating. RV1106 uses a 14 x 11 mm BGA313 package with 0.6 mm ball spacing. QFN heat dissipation depends on complete grounding of the bottom E-PAD. BGA provides greater peripheral expansion, while QFN is compact but has less thermal headroom.	RV1106G2/G3 suit compact products such as doorbells and small battery cameras. RV1106 targets expandable multi-camera designs. Hardware layout must provide proper grounding and heat dissipation.

RV1106G2 (QFN128 / 128MB SIP-DDR3L) is suitable for low-power battery devices, smart doorbells, and low-power IPCs. It supports up to 5MP at 30 FPS. External DDR routing is unnecessary, simplifying PCB design and reducing the system BOM cost. Due to memory-bandwidth limits, practical NPU performance is approximately 0.5 TOPS, which suits lightweight object detection and human detection.
RV1106G3 (QFN128 / 256MB SIP-DDR3L) also requires no external DDR. It provides the full 1 TOPS of NPU performance and supports 8MP image capture and encoding at 15 FPS. It is suitable for industrial scanning, high-resolution AI recognition, and wide-temperature DMS products. It offers the best overall price-performance ratio in the series.
RV1106 (BGA313 with external DDR) uses a BGA package and requires a complete DDR power supply and routing design. Memory capacity can be configured as needed. It suits multi-camera and high-bandwidth smart-retail vision equipment, although PCB layout is more difficult and total system cost is higher.

Long-Standby and Always-Online Design Approach

All-day operation with long standby time depends on AOV (Always on Video), multiple isolated power domains, and a fast wake-up mechanism. The hardware design must comply with the chip's absolute maximum ratings and recommended operating conditions.

AOV Mode and Multi-Level Power Scheduling: AOV combines continuous low-frame-rate capture with AI event triggering to meet the continuous monitoring requirements of battery-powered devices. During long standby, the MCU manages the sensor and image buffer while the Cortex-A7 and NPU enter deep sleep. Only essential power domains remain active, enabling low-frame-rate capture and encoding at 1 FPS. When a person, vehicle, or another target is detected, a hardware interrupt wakes the complete chip and switches the system to normal-frame-rate recording and AI inference.

Operating Mode	Core State	Typical Power	Battery Performance (5200mAh)
AOV Standby	RISC-V MCU running; A7/NPU asleep	Approximately 40 mW (engineering reference)	Approximately 14 days without sunlight (prototype reference)
Event Wake-Up	A7/NPU running at full speed with normal-frame-rate encoding	Dynamic load	Depends on event-trigger frequency
Continuous Recording	All modules active	Dynamic power	External power recommended

Complete Vision Data Processing and AI Inference Pipeline

Hardware direct-link architecture and MPP media framework: The RV1106 vision data path is VI (video input) - ISP - VENC/NPU through a direct hardware connection. The MPP media framework binds the VI channel directly to VENC/NPU, reducing CPU memory copies and bus load.

Video input interface hardware resources:

Two MIPI-CSI DPHY V1.2 interfaces, each with two lanes at 1.5 Gbps per lane. They can be combined into a four-lane interface.
One DVP interface running at up to 150 MHz, with support for BT.601, BT.656, and BT.1120.

After image preprocessing, the ISP outputs YUV data. VENC supports all six rate-control modes specified in the datasheet.

Boot storage options: SPI Flash, eMMC 4.51, and SD/MMC. Firmware can be downloaded through USB or UART.

On-chip memory: 256KB shared SRAM, 8KB PMU-SRAM, 20KB Boot ROM, and 8K-bit OTP.

2 RKNN Toolchain and Model Quantization Deployment: The NPU supports mixed INT4, INT8, and INT16 quantization, while RKNN-Toolkit2 performs model conversion. INT8 balances accuracy and speed, and INT4 reduces model size. A PaddleDetection object-detection rate of 25 FPS is an engineering test result. Deployment requires loading the RKNN model into the DDR memory pool and calling the inference interface through the C/C++ API.

3 Lightweight Vision Library Optimization: Embedded systems use the streamlined OpenCV-mobile library with GUI components removed to reduce size and accelerate startup. A hybrid architecture combining lightweight-library preprocessing with NPU inference reduces CPU utilization and fits the power budget of long-standby devices.

Stage	Core Module	Development Framework or Tool	Performance Optimization	Hardware Constraint
Image Capture	VI + MIPI-CSI/DVP	MPP SDK	Bind hardware paths to reduce memory-copy overhead	Supports up to three synchronized sensor inputs. RV1106G2 supports up to 5MP at 30 FPS.
Image Enhancement	ISP	Hardware register configuration	Enable hardware image acceleration such as HDR and 3DNR	ISP hardware supports time-division multiplexing of up to four sensors.
Video Encoding	VENC	MPP VENC API	Configure six rate-control modes and enable smart encoding	Maximum encoding bit rate is 60 Mbps.
AI Inference	NPU	RKNN-Toolkit2	Use mixed INT4, INT8, and INT16 quantization	Memory resources are limited by the integrated SIP DDR or external DDR configuration.
Vision Processing	Cortex-A7 CPU	OpenCV-mobile (streamlined version)	Remove unnecessary software modules to reduce system load	In AOV sleep mode, prioritize powering down the CPU.

Continuous Connectivity and System-Level Engineering Optimization

1 Dual-Mode Network Architecture and Smart Encoding Strategy

Hardware resources: Chip Integrated 10/100M Ethernet MAC and PHY (RMII Interface). An SDIO 3.0 interface supports external Wi-Fi and Bluetooth modules, and USB 2.0 OTG is integrated. Peripheral resources include five I2C interfaces, two SPI interfaces, six UART interfaces, and an I2S audio interface.

Ethernet provides a reliable wired backbone. An external Wi-Fi 6 and Bluetooth 5.2 module can be connected through SDIO for flexible wireless provisioning. Heartbeat reporting and automatic reconnection keep the network link available.

Smart Encoding 2.0 is an upper-layer SDK software algorithm that supports adaptive bit-rate adjustment. Compared with conventional CBR fixed-bit-rate operation, it can reduce bandwidth use and storage requirements.

The audio subsystem integrates a hardware audio codec with a dual-channel 24-bit ADC and a single-channel DAC. The typical signal-to-noise ratio is 90 dB, and both differential and single-ended microphone inputs are supported.

2 Linux System Optimization and Security Authentication

Buildroot is used to build the embedded Linux system, streamline the kernel and application services, and support OTA firmware updates.

The chip includes a complete hardware security engine with a hardware cryptographic unit supporting SHA-1, SHA-256, AES, DES, TDES, RSA, ECC, and SM2 algorithms, along with a true random-number generator and secure OTP. TrustZone and secure boot are supported. These functions enable firmware encryption, secure key storage, and hardware-software security-domain isolation for privacy protection in security products.

Typical Applications and Solution Integration Guide

Application	Core Requirement	Recommended Configuration	Key Interfaces	Hardware Constraint
Low-Power IPC or Smart Doorbell	Long-standby AOV and night vision	RV1106G2 SIP with 1Gb DDR3L	MIPI-CSI, SDIO Wi-Fi, RTC	Maximum 5MP at 30 FPS
Industrial Optical Barcode Scanner	High-speed capture and triggered acquisition	RV1106G3 SIP with 2Gb DDR3L	MIPI-CSI, UART, GPIO	Maximum 8MP at 15 FPS
Smart Retail or Smart Shelf	Multi-camera vision analysis	RV1106 BGA External DDR	Dual MIPI-CSI, Ethernet	Requires strict DDR power-supply design
In-Cabin DMS or Dashcam	Wide-temperature operation	RV1106G3	MIPI/DVP, Ethernet, USB OTG	Ambient temperature: -20 to 85 C; junction temperature: <=125 C

We provide RV1106-based PCBA hardware design and customized complete vision solutions, including schematic and PCB design, component selection, low-level driver adaptation, algorithm porting and debugging, and complete-system integration. For questions about chip selection, hardware design, software migration, performance optimization, or customized projects, contact us for technical support: [email protected]